Espressif Systems /ESP32-S2 /SPI0 /DMA_CONF

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Interpret as DMA_CONF

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (IN_RST)IN_RST 0 (OUT_RST)OUT_RST 0 (AHBM_FIFO_RST)AHBM_FIFO_RST 0 (AHBM_RST)AHBM_RST 0 (IN_LOOP_TEST)IN_LOOP_TEST 0 (OUT_LOOP_TEST)OUT_LOOP_TEST 0 (OUT_AUTO_WRBACK)OUT_AUTO_WRBACK 0 (OUT_EOF_MODE)OUT_EOF_MODE 0 (OUTDSCR_BURST_EN)OUTDSCR_BURST_EN 0 (INDSCR_BURST_EN)INDSCR_BURST_EN 0 (OUT_DATA_BURST_EN)OUT_DATA_BURST_EN 0 (MEM_TRANS_EN)MEM_TRANS_EN 0 (DMA_RX_STOP)DMA_RX_STOP 0 (DMA_TX_STOP)DMA_TX_STOP 0 (DMA_CONTINUE)DMA_CONTINUE 0 (SLV_LAST_SEG_POP_CLR)SLV_LAST_SEG_POP_CLR 0 (DMA_SLV_SEG_TRANS_EN)DMA_SLV_SEG_TRANS_EN 0 (SLV_RX_SEG_TRANS_CLR_EN)SLV_RX_SEG_TRANS_CLR_EN 0 (SLV_TX_SEG_TRANS_CLR_EN)SLV_TX_SEG_TRANS_CLR_EN 0 (RX_EOF_EN)RX_EOF_EN 0 (DMA_INFIFO_FULL_CLR)DMA_INFIFO_FULL_CLR 0 (DMA_OUTFIFO_EMPTY_CLR)DMA_OUTFIFO_EMPTY_CLR 0EXT_MEM_BK_SIZE 0 (DMA_SEG_TRANS_CLR)DMA_SEG_TRANS_CLR

Description

SPI DMA control register

Fields

IN_RST

The bit is used to reset in dma fsm and in data fifo pointer.

OUT_RST

The bit is used to reset out dma fsm and out data fifo pointer.

AHBM_FIFO_RST

Reset spi dma ahb master fifo pointer.

AHBM_RST

Reset spi dma ahb master.

IN_LOOP_TEST

Set bit to test in link.

OUT_LOOP_TEST

Set bit to test out link.

OUT_AUTO_WRBACK

when the bit is set, DMA continue to use the next inlink node when the length of inlink is 0.

OUT_EOF_MODE

out eof flag generation mode . 1: when dma pop all data from fifo 0:when ahb push all data to fifo.

OUTDSCR_BURST_EN

read descriptor use burst mode when read data for memory.

INDSCR_BURST_EN

read descriptor use burst mode when write data to memory.

OUT_DATA_BURST_EN

spi dma read data from memory in burst mode.

MEM_TRANS_EN

1: Internal memory data transfer enable bit. Send SPI DMA RX buffer data to SPI DMA TX buffer. 0: Disable this function.

DMA_RX_STOP

spi dma read data stop when in continue tx/rx mode.

DMA_TX_STOP

spi dma write data stop when in continue tx/rx mode.

DMA_CONTINUE

spi dma continue tx/rx data.

SLV_LAST_SEG_POP_CLR

1: Clear spi_slv_seg_frt_pop_mask. 0 : others

DMA_SLV_SEG_TRANS_EN

Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable.

SLV_RX_SEG_TRANS_CLR_EN

1: spi_dma_infifo_full_vld is cleared by spi slave CMD5. 0: spi_dma_infifo_full_vld is cleared by SPI_TRANS_DONE.

SLV_TX_SEG_TRANS_CLR_EN

1: spi_dma_outfifo_empty_vld is cleared by spi slave CMD6. 0: spi_dma_outfifo_empty_vld is cleared by SPI_TRANS_DONE.

RX_EOF_EN

1: SPI_IN_SUC_EOF_INT_RAW is set when the number of dma pushed data bytes is equal to the value of SPI_SLV_DMA_RD_BYTELEN[19:0]/ SPI_MST_DMA_RD_BYTELEN[19:0] in spi dma transition. 0: SPI_IN_SUC_EOF_INT_RAW is set by SPI_TRANS_DONE in non-seg-trans or SPI_DMA_SEG_TRANS_DONE in seg-trans.

DMA_INFIFO_FULL_CLR

1:Clear spi_dma_infifo_full_vld. 0: Do not control it.

DMA_OUTFIFO_EMPTY_CLR

1:Clear spi_dma_outfifo_empty_vld. 0: Do not control it.

EXT_MEM_BK_SIZE

Select the external memory block size.

DMA_SEG_TRANS_CLR

1: End slave seg-trans, which acts as 0x05 command. 2 or more end seg-trans signals will induce error in DMA RX. 0: others. Will be cleared in 1 APB CLK cycles by hardware…

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